In the field of optical transmission, 40 Gbps lines have recently begun to be introduced as further increases are made in network speed and bandwidth. When receiving an optical signal, waveform distortion of the optical signal increases in magnitude, due to the dispersion characteristics of the fiber cable or other optical transmission line. The influence of this waveform distortion on optical transmission increases more or less proportionally with the square of the transmission speed. For this reason, technology for mitigating a wavelength dispersion value becomes more and more important as the transmission speed of the optical signal increases.
FIG. 12 illustrates an optical receiver in accordance with the related art, wherein technology for mitigating a wavelength dispersion value has been adopted. As illustrated in FIG. 12, the optical receiver 10 of the related art includes an optical amplifier 11, a variable dispersion mitigator (VDM) 12, a delay interferometer 13, a light detector 14, an amplifier 15, and a Serializer/Deserializer (SerDes) 16. In addition, the optical receiver 10 of the related art includes a framer 17, a VDM controller 18, and a clock recovery unit (CR) 19.
In the optical receiver 10 in accordance with the related art, the optical amplifier 11 amplifies an optical signal input from an optical transmission line. The VDM 12 mitigates a wavelength dispersion value in the amplified optical signal. The delay interferometer 13 demodulates the mitigated optical signal. Subsequently, the light detector 14 converts the demodulated optical signal into an electrical signal. The amplifier 15 amplifies the converted electrical signal. The CR 19 generates a clock synchronized with the phase of the clock contained in the input electrical signal. The SerDes 16 then identifies the electrical signal as being 0 or 1 data, based on the clock generated by the CR 19 (hereinafter referred to as the internal clock), and outputs an incoming data signal expressing the identification results to the framer 17.
Based on the internal clock from the CR 19, the framer 17 corrects errors in the incoming data signal from the SerDes 16, and outputs the corrected incoming data signal to an external apparatus. In addition, the framer 17 detects an error correction count, which expresses the number of errors that were corrected in the incoming data signal from the SerDes 16. The detected error correction count is output to the VDM controller 18.
The VDM controller 18 sets an optimal dispersion value by adjusting the dispersion value set in the VDM 12 so as to minimize the error correction count detected by the framer 17. FIG. 13 illustrates the relationship between the dispersion value and the error correction count. As illustrated in FIG. 13, the error correction count increases as the dispersion value moves farther away from the optimal value. If the error correction count exceeds a threshold value T corresponding to the dispersion tolerance, then communication will be impaired. The VDM controller 18 positively or negatively adjusts the dispersion value in the VDM 12 so as to minimize the error correction count.
Meanwhile, the relationship between the dispersion value and the error correction count changes in cases where the quality of the transmitted optical signal is favorable and where the optical signal-to-noise ratio (OSNR) is favorable. FIG. 14 illustrates the relationship between the dispersion value and the error correction count in the case where the OSNR is favorable. As illustrated in FIG. 14, when the OSNR is favorable, the rate of increase in the error correction count in response to changes in the dispersion value becomes greater than usual near the dispersion tolerance. Consequently, in the vicinity of the dispersion tolerance, the error correction count might increase drastically as a result of the VDM controller 18 making a slight adjustment to the dispersion value in the VDM 12. If the error correction count increases drastically, the CR 19 will enter what is referred to as the unlocked state. The unlocked state refers to the state wherein the output signal of the CR 19 is not synchronized with the phase (or the frequency) of the input signal.
The reason why such an unlocked state occurs will now be explained using FIGS. 15 and 16. FIG. 15 illustrates one example of an electrical signal input into the CR 19 before adjusting the dispersion value. In FIG. 15, the vertical axis represents the electrical signal power, while the horizontal axis represents the electrical signal frequency. As illustrated in FIG. 15, the electrical signal input into the CR 19 contains a clock component of a given frequency. For example, the electrical signal in FIG. 15 contains a clock component at a frequency of 40 GHz.
Now assume that the VDM controller 18 adjusts the dispersion value in the VDM 12 near the dispersion tolerance. In so doing, the error correction count will increase drastically. FIG. 16 illustrates one example of an electrical signal input into the CR 19 after adjusting the dispersion value. As illustrated in FIG. 16, once the dispersion value is adjusted, the clock component contained in the electrical signal input into the CR 19 momentarily attenuates. In the example illustrated in FIG. 16, the clock component at a frequency of 40 GHz momentarily attenuates. As a result of such attenuation of the clock component, the input signal into the voltage-controlled oscillator (VCO) inside the CR 19 momentarily fluctuates, and the VCO stops correctly generating the internal clock. For this reason, the CR 19 enters an unlocked state.
At this point, the unlocked CR 19 cannot supply an accurate internal clock to other components such as the SerDes 16 and the framer 17. As a result, the dispersion value in the VDM 12 settles at the dispersion tolerance, and communication might be impaired regardless of whether or not the error correction count is less than or equal to the threshold value T.
For this reason, various technologies for avoiding the unlocked state when adjusting the dispersion value have been proposed recently. For example, in one technique, another threshold value U that is smaller than the threshold value T is separately set near the dispersion tolerance. When the error correction count has exceeded the threshold value U, adjustment of the dispersion value is temporarily suspended. In another technique, the adjustment step value for single adjustments of the dispersion value is decreased.
However, related art that adjusts the dispersion value by using the above two threshold values requires a process for changing settings between the threshold values, as well as a process for suspending adjustment of the dispersion value. For this reason, there is a problem in that the dispersion value adjustment process becomes more complicated overall. Meanwhile, in related art that decreases the dispersion value adjustment step value, the time until the dispersion value reaches the optimal value increases to the degree that the dispersion value adjustment step value is decreased. For this reason, there is a problem in that the dispersion value adjustment process becomes delayed. Technology related to the foregoing is disclosed in Japanese Unexamined Patent Application Publication No. 2007-306371.